Creating a makefile

This is fairly simple: just create a text file using any text editor. The makefile just contains a list of file dependencies and commands needed to satisfy them.

Lets look at an example makefile:

Make would interpret the file as follows:

1. prog depends on 3 files: prog.o, f1.o and f2.o. If any of the object files have been changed since last compilation the files must be relinked.

2. prog.o depends on 2 files. If these have been changed prog.o must be recompiled. Similarly for f1.o and f2.o.

The last 3 commands in the makefile are called explicit rules - since the files in commands are listed by name.

We can use implicit rules in our makefile which let us generalise our rules and save typing.

We can take

and generalise to this:

.c.o: ~cc -c $< We read this as .source_extension.target_extension: command

$< is shorthand for file name with .c extension.

We can put comments in a makefile by using the #symbol. All characters following #on line are ignored.

Make has many built in commands similar to or actual UNIX commands. Here are a few:

There are many more see manual pages for make (online and printed reference)